MEMBER 한양대학교 나노전자소자 및 재료연구실

NEDML PROFESSOR

최창환 ( Changhwan Choi, 崔暢桓 ), Ph.D
Professor, Division Chair, Director
Division of Materials Science and Engineering, Hanyang University
Division of Nanoscale Semiconductor Engineering, Hanyang University
Research Institute of Industrial Materials Technology
Office: Room 411, Advanced Materials Science and Engineering Building
Address: Division of Materials Science and Engineering, Hanyang University
17 Haengdang-dong, Seongdong-gu, Seoul 04763, Korea
Tel: +82-2-2220-0383
Fax: +82-2-2220-0389
Email: cchoi@hanyang.ac.kr

Education

05/2006 Ph.D, Electrical & Computer Engineering, The University of Texas at Austin, USA
Dissertation: “The effects of Si, N and O incorporation and oxygen-scavenging technique on performance of Hf-based gate dielectric MOSFETs”
Advisor: Prof. Jack C. Lee
12/2002 M.S, Materials Science & Engineering, The University of Texas at Austin, USA
Thesis: “Thermally stable advanced ultra-thin CVD hafnium oxynitride (HfOxNy) gate dielectrics with poly-Si gate electrode for future CMOS technology”
Advisor: Prof. Dim-Lee Kwong
02/2000 B.S, Materials Science & Engineering, Hanyang University, Seoul, Korea

Work Experiences

03/2010 - Current Professor, Division Head, Director
Division of Materials Science and Engineering
Division of Nanoscale Semiconductor Engineering
Research Institute of Industrial Materials Technology
Hanyang University, Seoul, Korea
02/2016 - 02/2017 Visiting Research Professor
Center for Spintronics, Korea Institute of Science and Technology (KIST), Seoul, Korea
01/2006 - 02/2010 Research Staff Member (Full Time)
IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA
06/2005 - 09/2005 Academic Internship
APRDL [Advanced Products Research & Development Laboratory]
Freescale Semiconductor (Former Motorola Semiconductor), Austin, TX, USA
01/2001 - 12/2005 Graduate Research Assistant
Microelectronics Research Center, The University of Texas at Austin, Austin, TX, USA
08/2000 - 12/2000 Research Assistant
The University of Wisconsin at Madison, Madison, WI, USA

Research Interests

Nano-electronic devices, materials and process development for advanced semiconductor, display, storage and energy applications
Semiconductor Si Device Fabrication & Characterization, Advanced Logic & Memory Technology, 3D Device (FINFET, GAAFET), Low-Power Device (TFET, NCFET, FeFET), V-NAND Flash Memory Device, Wide Band-Gap SiC & GaN Power Semiconducdtor, Non-Si Substrate, Post-Si Devices, Neuromorphic Device, 3D Integration
Photovoltaic Thin Film Compound Solar Cell, Quantum Dot Solar Cell, Transparent Conducting Oxide
Display ALD Oxide TFT
Thin Film
Technology		 Metal Oxide Thin Film, Thermoelectric Materials, Organic/Inorganic Hybrid Film, Nano-Patterning

Awards

2019 Minister Award, The Ministry of Science and ICT (과학기술정통부 장관상)
2018 Best Paper Award [Si & Group IV Device Integration] - Korean Conference on Semiconductors (KCS)
2015 Best Poster Award - Korean Conference on Semiconductors (KCS)
2014 Prize -International Conference Electronic Materials and Nanotechnology for Green Enviroment (ENGE)
Best Poster Award - Nano-Imprint-Molding-Print Forum
2013 Young Scientist Award (Technology) - KIMM (Korean Institute of Metals and Materials)
Good Patent Award - SK Hynix Semiconductor
2007 & 2009 IBM Invention Achievement
2001 - 2005 SRC (Semiconductor Research Corporation) Scholarship & Intel Scholarship
2000 Department Fellowship, The University of Wisconsin at Madison

Members

IEEE (Institute of Electrical and Electronics Engineers)
MRS (Materials Research Society)
KIMM (Korean Institute of Metals and Materials)
K-MRS (Materials Research Society of Korea), Editorial Board
IEIE (The Instiute of Electronics and Information Engineers)
KMEPS (The Korean Microelecronics and Packaging Society)
KONTRS (Korea Nanotechnology Research Society)
KSEA (Korean-American Scientists and Engineers Association)

Publications

International: 77
Domestic: 5

Patents

[Registration] by. May 2016
  • Field-Effect Transistor Device Having a Metal Gate Stack with an Oxygen Barrier Layer, US patent 8415677
  • Structure And Method To Obtain EOT Scaled Dielectric Stacks, US patent 9059314
  • Scaled Equivalent Oxide Thickness For Field Effect Transistor Devices, US patent 8343839
  • Scavenging Metal Stack For A High-k Gate Dielectric, US patent 7989902
  • Method and Apparatus For Fabricating A High-performance Band-edge Complementary Metal-oxide-semiconductor Device, US patent 8097500
  • Structure And Method To Obtain EOT Scaled Dielectric Stacks, US patent 8304836
  • Scavenging Metal Stack For A High-k Gate Dielectric, US patent 8367496
  • Scaled Equivalent Oxide Thickness For Field Effect Transistor Devices, US patent 8716813
  • Low Threshold Voltage CMOS Device, US patent 8941184
  • Fabrication of Low Threshold Voltage and Inversion Oxide Thickness Scaling for a High-K Metal Gate P-type MOSFET, US patent 9105745
  • Scaled Equivalent Oxide Thickness for Field Effect Transistor Devices, US patent 8940599
  • Low Threshold Voltage CMOS Device, US patent 9263344
  • Semiconductor Device and Method of Manufacturing the Same, US patent 9013000
  • A Semiconductor Device and Method of Manufacturing the Same, US patent 9177869
  • Semiconductor Device and Method of Manufacturing the Same, US patent 9312190
  • 저항 메모리 소자에서의 전극 생성 방법, KR patent 10-1570605
  • 나노 금속 라인 생성 방법, KR patent 10-1604912
  • 나노 전극층 생성 방법, KR patent 10-1618436
3 US patents applied, 1 Taiwan patent applied, 1 China patent applied, 5 Korean patent applied

Lectues

Undergraduate Materials Science Engineering, Electronic Device Materials I/II,
Energy Materials, Semiconductor Process Technology
Graduate Thin Film Technology, Advanced Semiconductor Device Physics,
Advanced Semiconductor Fabrication Technology, Materials and Devices for Photovoltaic